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altera corporation 1 max 3000a programmable logic device family december 2002, ver. 3.2 data sheet ds-max3000a-3.2 features... high?performance, low?cost cmos eeprom?based programmable logic devices (plds) built on a max ? architecture (see table 1 ) 3.3-v in-system programmability (isp) through the built?in ieee std. 1149.1 joint test action group (jtag) interface with advanced pin-locking capability ? isp circuitry compliant with ieee std. 1532 built?in boundary-scan test (bst) circuitry compliant with ieee std. 1149.1-1990 enhanced isp features: ? enhanced isp algorithm for faster programming ? isp_done bit to ensure complete programming ? pull-up resistor on i/o pins during in?system programming high?density plds ranging from 600 to 10,000 usable gates 4.5?ns pin?to?pin logic delays with counter frequencies of up to 227.3 mhz multivolt tm i/o interface enabling the device core to run at 3.3 v, while i/o pins are compatible with 5.0?v, 3.3?v, and 2.5?v logic levels pin counts ranging from 44 to 256 in a variety of thin quad flat pack (tqfp), plastic quad flat pack (pqfp), plastic j?lead chip carrier (plcc), and fineline bga tm packages hot?socketing support programmable interconnect array (pia) continuous routing structure for fast, predictable performance table 1. max 3000a device features feature epm3032a epm3064a epm3128a epm3256a epm3512a usable gates 600 1,250 2,500 5,000 10,000 macrocells 32 64 128 256 512 logic array blocks 2 4 8 16 32 maximum user i/o pins 34 66 96 158 208 t pd (ns) 4.5 4.5 5.0 7.5 7.5 t su (ns) 2.9 2.8 3.3 5.2 5.6 t co1 (ns) 3.0 3.1 3.4 4.8 4.7 f cnt (mhz) 227.3 222.2 192.3 126.6 116.3
2 altera corporation max 3000a programmable logic device family data sheet ...and more features pci compatible bus?friendly architecture including programmable slew?rate control open?drain output option programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls programmable power?saving mode for a power reduction of over 50 % in each macrocell configurable expander product?term distribution, allowing up to 32 product terms per macrocell programmable security bit for protection of proprietary designs enhanced architectural features, including: ? 6 or 10 pin? or logic?driven output enable signals ? two global clock signals with optional inversion ? enhanced interconnect resources for improved routability ? programmable output slew?rate control software design support and automatic place?and?route provided by altera?s development systems for windows?based pcs and sun sparcstations, and hp 9000 series 700/800 workstations additional design entry and simulation support provided by edif 2 0 0 and 3 0 0 netlist files, library of parameterized modules (lpm), verilog hdl, vhdl, and other interfaces to popular eda tools from third?party manufacturers such as cadence, exemplar logic, mentor graphics, orcad, synopsys, synplicity, and veribest programming support with the altera master programming unit (mpu), masterblaster tm communications cable, byteblastermv tm parallel port download cable, bitblaster tm serial download cable as well as programming hardware from third?party manufacturers and any in?circuit tester that supports jam tm standard test and programming language (stapl) files ( .jam ), jam stapl byte-code files ( .jbc ), or serial vector format files ( .svf ) general description max 3000a devices are low?cost, high?performance devices based on the altera max architecture. fabricated with advanced cmos technology, the eeprom?based max 3000a devices operate with a 3.3-v supply voltage and provide 600 to 10,000 usable gates, isp, pin-to-pin delays as fast as 4.5 ns, and counter speeds of up to 227.3 mhz. max 3000a devices in the ?4, ?5, ?6, ?7, and ?10 speed grades are compatible with the timing requirements of the pci special interest group (pci sig) pci local bus specification, revision 2.2 . see table 2 .
altera corporation 3 max 3000a programmable logic device family data sheet the max 3000a architecture supports 100 % transistor-to-transistor logic (ttl) emulation and high?density small-scale integration (ssi), medium-scale integration (msi), and large-scale integration (lsi) logic functions. the max 3000a architecture easily integrates multiple devices ranging from pals, gals, and 22v10s to mach and plsi devices. max 3000a devices are available in a wide range of packages, including plcc, pqfp, and tqfp packages. see table 3 . note: (1) when the ieee std. 1149.1 (jtag) interface is used for in?system programming or boundary?scan testing, four i/o pins become jtag pins. max 3000a devices use cmos eeprom cells to implement logic functions. the user?configurable max 3000a architecture accommodates a variety of independent combinatorial and sequential logic functions. the devices can be reprogrammed for quick and efficient iterations during design development and debugging cycles, and can be programmed and erased up to 100 times. table 2. max 3000a speed grades device speed grade ?4 ?5 ?6 ?7 ?10 epm3032a vvv epm3064a vvv epm3128a vvv epm3256a vv epm3512a vv table 3. max 3000a maximum user i/o pins note (1) device 44?pin plcc 44?pin tqfp 100?pin tqfp 144?pin tqfp 208?pin pqfp 256-pin fineline bga epm3032a 34 34 epm3064a 34 34 66 epm3128a 80 96 epm3256a 116 158 epm3512a 172 208
4 altera corporation max 3000a programmable logic device family data sheet max 3000a devices contain 32 to 512 macrocells, combined into groups of 16 macrocells called logic array blocks (labs). each macrocell has a programmable? and /fixed? or array and a configurable register with independently programmable clock, clock enable, clear, and preset functions. to build complex logic functions, each macrocell can be supplemented with shareable expander and high?speed parallel expander product terms to provide up to 32 product terms per macrocell. max 3000a devices provide programmable speed/power optimization. speed?critical portions of a design can run at high speed/full power, while the remaining portions run at reduced speed/low power. this speed/power optimization feature enables the designer to configure one or more macrocells to operate at 50 % or lower power while adding only a nominal timing delay. max 3000a devices also provide an option that reduces the slew rate of the output buffers, minimizing noise transients when non?speed?critical signals are switching. the output drivers of all max 3000a devices can be set for 2.5 v or 3.3 v, and all input pins are 2.5?v, 3.3?v, and 5.0-v tolerant, allowing max 3000a devices to be used in mixed?voltage systems. max 3000a devices are supported by altera development systems, which are integrated packages that offer schematic, text?including vhdl, verilog hdl, and the altera hardware description language (ahdl)?and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. the software provides edif 2 0 0 and 3 0 0, lpm, vhdl, verilog hdl, and other interfaces for additional design entry and simulation support from other industry?standard pc? and unix?workstation?based eda tools. the software runs on windows?based pcs, as well as sun sparcstation, and hp 9000 series 700/800 workstations. f for more information on development tools, see the max+plus ii programmable logic development system & software data sheet and the quartus programmable logic development system & software data sheet . functional description the max 3000a architecture includes the following elements: logic array blocks (labs) macrocells expander product terms (shareable and parallel) programmable interconnect array (pia) i/o control blocks the max 3000a architecture includes four dedicated inputs that can be used as general?purpose inputs or as high?speed, global control signals (clock, clear, and two output enable signals) for each macrocell and i/o pin. figure 1 shows the architecture of max 3000a devices.
altera corporation 5 max 3000a programmable logic device family data sheet figure 1. max 3000a device block diagram note: (1) epm3032a, epm3064a, epm3128a, and epm3256a devices have six output enables. epm3512a devices have 10 output enables. logic array blocks the max 3000a device architecture is based on the linking of high?performance labs. labs consist of 16?macrocell arrays, as shown in figure 1 . multiple labs are linked together via the pia, a global bus that is fed by all dedicated input pins, i/o pins, and macrocells. each lab is fed by the following signals: 36 signals from the pia that are used for general logic inputs global controls that are used for secondary register functions 6 or 10 6 or 10 input/gclrn 6 or 10 output enables (1) 6 or 10 output enables (1) 16 36 36 16 i/o control block lab c lab d i/o control block 6 or 10 16 36 36 16 i/o control block lab a macrocells 1 to 16 lab b i/o control block 6 or 10 pia input/gclk1 input/oe2/gclk2 input/oe1 2 to 16 i/o 2 to 16 i/o 2 to 16 i/o 2 to 16 i/o 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 2 to 16 macrocells 17 to 32 macrocells 33 to 48 macrocells 49 to 64
6 altera corporation max 3000a programmable logic device family data sheet macrocells max 3000a macrocells can be individually configured for either sequential or combinatorial logic operation. macrocells consist of three functional blocks: logic array, product?term select matrix, and programmable register. figure 2 shows a max 3000a macrocell. figure 2. max 3000a macrocell combinatorial logic is implemented in the logic array, which provides five product terms per macrocell. the product?term select matrix allocates these product terms for use as either primary logic inputs (to the or and xor gates) to implement combinatorial functions, or as secondary inputs to the macrocell?s register preset, clock, and clock enable control functions. two kinds of expander product terms (?expanders?) are available to supplement macrocell logic resources: shareable expanders, which are inverted product terms that are fed back into the logic array parallel expanders, which are product terms borrowed from adjacent macrocells the altera development system automatically optimizes product?term allocation according to the logic requirements of the design. product - t erm s elect matri x 36 s ignals f rom pia 16 expander product terms lab local arra y parallel logic expanders ( from other macrocells ) s hared lo g ic expanders clear select global clear global clocks clock/ enable select 2 prn c lr n q ena register b y pass t o i/o c ontrol bloc k t o pia pro g rammable re g iste r vcc d/t
altera corporation 7 max 3000a programmable logic device family data sheet for registered functions, each macrocell flipflop can be individually programmed to implement d, t, jk, or sr operation with programmable clock control. the flipflop can be bypassed for combinatorial operation. during design entry, the designer specifies the desired flipflop type; the altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. each programmable register can be clocked in three different modes: global clock signal mode, which achieves the fastest clock?to?output performance. global clock signal enabled by an active?high clock enable. a clock enable is generated by a product term. this mode provides an enable on each flipflop while still achieving the fast clock?to?output performance of the global clock. array clock implemented with a product term. in this mode, the flipflop can be clocked by signals from buried macrocells or i/o pins. two global clock signals are available in max 3000a devices. as shown in figure 1 , these global clock signals can be the true or the complement of either of the two global clock pins, gclk1 or gclk2 . each register also supports asynchronous preset and clear functions. as shown in figure 2 , the product?term select matrix allocates product terms to control these operations. although the product?term?driven preset and clear from the register are active high, active?low control can be obtained by inverting the signal within the logic array. in addition, each register clear function can be individually driven by the active?low dedicated global clear pin ( gclrn ). expander product terms although most logic functions can be implemented with the five product terms available in each macrocell, highly complex logic functions require additional product terms. another macrocell can be used to supply the required logic resources. however, the max 3000a architecture also offers both shareable and parallel expander product terms (?expanders?) that provide additional product terms directly to any macrocell in the same lab. these expanders help ensure that logic is synthesized with the fewest possible logic resources to obtain the fastest possible speed.
8 altera corporation max 3000a programmable logic device family data sheet shareable expanders each lab has 16 shareable expanders that can be viewed as a pool of uncommitted single product terms (one from each macrocell) with inverted outputs that feed back into the logic array. each shareable expander can be used and shared by any or all macrocells in the lab to build complex logic functions. shareable expanders incur a small delay ( t sexp ). figure 3 shows how shareable expanders can feed multiple macrocells. figure 3. max 3000a shareable expanders shareable expanders can be shared by any or all macrocells in an lab. parallel expanders parallel expanders are unused product terms that can be allocated to a neighboring macrocell to implement fast, complex logic functions. parallel expanders allow up to 20 product terms to directly feed the macrocell or logic, with five product terms provided by the macrocell and 15 parallel expanders provided by neighboring macrocells in the lab. macrocell product-ter m logic pr oduc t- t erm select matrix macrocell product-ter m logic 36 s i g nals f rom pia 16 s hare d expanders
altera corporation 9 max 3000a programmable logic device family data sheet the altera development system compiler can automatically allocate up to three sets of up to five parallel expanders to the macrocells that require additional product terms. each set of five parallel expanders incurs a small, incremental timing delay ( t pexp ). for example, if a macrocell requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders; the first set includes five product terms, and the second set includes four product terms, increasing the total delay by 2 t pexp . two groups of eight macrocells within each lab (e.g., macrocells 1 through 8 and 9 through 16) form two chains to lend or borrow parallel expanders. a macrocell borrows parallel expanders from lower? numbered macrocells. for example, macrocell 8 can borrow parallel expanders from macrocell 7, from macrocells 7 and 6, or from macrocells 7, 6, and 5. within each group of eight, the lowest?numbered macrocell can only lend parallel expanders and the highest?numbered macrocell can only borrow them. figure 4 shows how parallel expanders can be borrowed from a neighboring macrocell. figure 4. max 3000a parallel expanders unused product terms in a macrocell can be allocated to a neighboring macrocell. preset clock clear product - er s elec t m atri x preset clock clear product - t er t t m s elec t matri x macrocell product- term logic from previous m acrocel l to next macrocell macrocell product- term logic 36 signals from pia 16 shared expanders
10 altera corporation max 3000a programmable logic device family data sheet programmable interconnect array logic is routed between labs on the pia. this global bus is a programmable path that connects any signal source to any destination on the device. all max 3000a dedicated inputs, i/o pins, and macrocell outputs feed the pia, which makes the signals available throughout the entire device. only the signals required by each lab are actually routed from the pia into the lab. figure 5 shows how the pia signals are routed into the lab. an eeprom cell controls one input to a two-input and gate, which selects a pia signal to drive into the lab. figure 5. max 3000a pia routing while the routing delays of channel?based routing schemes in masked or fpgas are cumulative, variable, and path?dependent, the max 3000a pia has a predictable delay. the pia makes a design?s timing performance easy to predict. i/o control blocks the i/o control block allows each i/o pin to be individually configured for input, output, or bidirectional operation. all i/o pins have a tri?state buffer that is individually controlled by one of the global output enable signals or directly connected to ground or v cc . figure 6 shows the i/o control block for max 3000a devices. the i/o control block has 6 or 10 global output enable signals that are driven by the true or complement of two output enable signals, a subset of the i/o pins, or a subset of the i/o macrocells. to lab pia signals
altera corporation 11 max 3000a programmable logic device family data sheet figure 6. i/o control block of max 3000a devices note: (1) epm3032a, epm3064a, epm3128a, and epm3256a devices have six output enables. epm3512a devices have 10 output enables. when the tri?state buffer control is connected to ground, the output is tri-stated (high impedance), and the i/o pin can be used as a dedicated input. when the tri?state buffer control is connected to v cc , the output is enabled. the max 3000a architecture provides dual i/o feedback, in which macrocell and pin feedbacks are independent. when an i/o pin is configured as an input, the associated macrocell can be used for buried logic. from macrocell slew-rate control to pia to other i/o pins 6 or 10 global output enable signals (1) pia vcc open-drain output oe select multiplexer gnd
12 altera corporation max 3000a programmable logic device family data sheet in?system programma- bility max 3000a devices can be programmed in?system via an industry? standard four?pin ieee std. 1149.1-1990 (jtag) interface. in-system programmability (isp) offers quick, efficient iterations during design development and debugging cycles. the max 3000a architecture internally generates the high programming voltages required to program its eeprom cells, allowing in?system programming with only a single 3.3?v power supply. during in?system programming, the i/o pins are tri?stated and weakly pulled?up to eliminate board conflicts. the pull?up value is nominally 50 k ? . max 3000a devices have an enhanced isp algorithm for faster programming. these devices also offer an isp_done bit that ensures safe operation when in?system programming is interrupted. this isp_done bit, which is the last bit programmed, prevents all i/o pins from driving until the bit is programmed. isp simplifies the manufacturing flow by allowing devices to be mounted on a printed circuit board (pcb) with standard pick?and?place equipment before they are programmed. max 3000a devices can be programmed by downloading the information via in?circuit testers, embedded processors, the masterblaster communications cable, the byteblastermv parallel port download cable, and the bitblaster serial download cable. programming the devices after they are placed on the board eliminates lead damage on high?pin?count packages (e.g., qfp packages) due to device handling. max 3000a devices can be reprogrammed after a system has already shipped to the field. for example, product upgrades can be performed in the field via software or modem. the jam stapl programming and test language can be used to program max 3000a devices with in?circuit testers, pcs, or embedded processors. f for more information on using the jam stapl programming and test language, see application note 88 (using the jam language for isp & icr via an embedded processor) , application note 122 (using jam stapl for isp & icr via an embedded processor) and an 111 (embedded programming using the 8051 and jam byte-code) . the isp circuitry in max 3000a devices is compliant with the ieee std. 1532 specification. the ieee std. 1532 is a standard developed to allow concurrent isp between multiple pld vendors. programming with external hardware max 3000a devices can be programmed on windows?based pcs with an altera logic programmer card, mpu, and the appropriate device adapter. the mpu performs continuity checking to ensure adequate electrical contact between the adapter and the device. f for more information, see the altera programming hardware data sheet .
altera corporation 13 max 3000a programmable logic device family data sheet the altera software can use text? or waveform?format test vectors created with the altera text editor or waveform editor to test the programmed device. for added design verification, designers can perform functional testing to compare the functional device behavior with the results of simulation. data i/o, bp microsystems, and other programming hardware manufacturers also provide programming support for altera devices. f for more information, see programming hardware manufacturers . ieee std. 1149.1 (jtag) boundary?scan support max 3000a devices include the jtag bst circuitry defined by ieee std. 1149.1?1990. table 4 describes the jtag instructions supported by max 3000a devices. the pin-out tables found on the altera web site ( http://www.altera.com ) or the altera digital library show the location of the jtag control pins for each device. if the jtag interface is not required, the jtag pins are available as user i/o pins. the instruction register length of max 3000a devices is 10 bits. the idcode and usercode register length is 32 bits. tables 5 and 6 show the boundary?scan register length and device idcode information for max 3000a devices. table 4. max 3000a jtag instructions jtag instruction description sample/preload allows a snapshot of signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern output at the device pins extest allows the external circuitry and board?evel interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins bypass places the 1bit bypass register between the tdi and tdo pins, which allows the bst data to pass synchronously through a selected device to adjacent devices during normal device operation idcode selects the idcode register and places it between the tdi and tdo pins, allowing the idcode to be serially shifted out of tdo usercode selects the 32?it usercode register and places it between the tdi and tdo pins, allowing the usercode value to be shifted out of tdo isp instructions these instructions are used when programming max 3000a devices via the jtag ports with the masterblaster, byteblastermv, or bitblaster cable, or when using a jam stapl file, jbc file, or svf file via an embedded processor or test equipment
14 altera corporation max 3000a programmable logic device family data sheet notes: (1) the most significant bit (msb) is on the left. (2) the least significant bit (lsb) for all jtag idcodes is 1 . f see application note 39 (ieee 1149.1 (jtag) boundary?scan testing in altera devices) for more information on jtag bst. table 5. max 3000a boundary?scan register length device boundary?scan register length epm3032a 96 epm3064a 192 epm3128a 288 epm3256a 480 epm3512a 624 table 6. 32?bit max 3000a device idcode value note (1) device idcode (32 bits) version (4 bits) part number (16 bits) manufacturer?s identity (11 bits) 1 (1 bit) (2) epm3032a 0001 0111 0000 0011 0010 00001101110 1 epm3064a 0001 0111 0000 0110 0100 00001101110 1 epm3128a 0001 0111 0001 0010 1000 00001101110 1 epm3256a 0001 0111 0010 0101 0110 00001101110 1 epm3512a 0001 0111 0101 0001 0010 00001101110 1
altera corporation 15 max 3000a programmable logic device family data sheet figure 7 shows the timing information for the jtag signals. figure 7. max 3000a jtag waveforms table 7 shows the jtag timing parameters and values for max 3000a devices. table 7. jtag timing parameters & values for max 3000a devices symbol parameter min max unit t jcp tck clock period 100 ns t jch tck clock high time 50 ns t jcl tck clock low time 50 ns t jpsu jtag port setup time 20 ns t jph jtag port hold time 45 ns t jpco jtag port clock to output 25 ns t jpzx jtag port high impedance to valid output 25 ns t jpxz jtag port valid output to high impedance 25 ns t jssu capture register setup time 20 ns t jsh capture register hold time 45 ns t jsco update register clock to output 25 ns t jszx update register high impedance to valid output 25 ns t jsxz update register valid output to high impedance 25 ns tdo tck t jpzx t jpco t jph t jpxz t jcp t jpsu t jcl t jch tdi tms signal to be captured signal to be driven t jszx t jssu t jsh t jsco t jsxz
16 altera corporation max 3000a programmable logic device family data sheet programmable speed/power control max 3000a devices offer a power?saving mode that supports low-power operation across user?defined signal paths or the entire device. this feature allows total power dissipation to be reduced by 50 % or more because most logic applications require only a small fraction of all gates to operate at maximum frequency. the designer can program each individual macrocell in a max 3000a device for either high?speed or low?power operation. as a result, speed-critical paths in the design can run at high speed, while the remaining paths can operate at reduced power. macrocells that run at low power incur a nominal timing delay adder ( t lpa ) for the t lad , t lac , t ic , t acl , t en , t cppw and t sexp parameters. output configuration max 3000a device outputs can be programmed to meet a variety of system?level requirements. multivolt i/o interface the max 3000a device architecture supports the multivolt i/o interface feature, which allows max 3000a devices to connect to systems with differing supply voltages. max 3000a devices in all packages can be set for 2.5?v, 3.3?v, or 5.0?v i/o pin operation. these devices have one set of v cc pins for internal operation and input buffers ( vccint ), and another set for i/o output drivers ( vccio ). the vccio pins can be connected to either a 3.3?v or 2.5?v power supply, depending on the output requirements. when the vccio pins are connected to a 2.5?v power supply, the output levels are compatible with 2.5?v systems. when the vccio pins are connected to a 3.3?v power supply, the output high is at 3.3 v and is therefore compatible with 3.3-v or 5.0?v systems. devices operating with v ccio levels lower than 3.0 v incur a nominally greater timing delay of t od2 instead of t od1 . inputs can always be driven by 2.5?v, 3.3?v, or 5.0?v signals. table 8 summarizes the max 3000a multivolt i/o support. note: (1) when v ccio is 3.3 v, a max 3000a device can drive a 2.5?v device that has 3.3?v tolerant inputs. table 8. max 3000a multivolt i/o support v ccio voltage input signal (v) output signal (v) 2.5 3.3 5.0 2.5 3.3 5.0 2.5 vvvv 3.3 vvvvvv
altera corporation 17 max 3000a programmable logic device family data sheet open?drain output option max 3000a devices provide an optional open?drain (equivalent to open-collector) output for each i/o pin. this open?drain output enables the device to provide system?level control signals (e.g., interrupt and write enable signals) that can be asserted by any of several devices. it can also provide an additional wired? or plane. open-drain output pins on max 3000a devices (with a pull-up resistor to the 5.0-v supply) can drive 5.0-v cmos input pins that require a high v ih . when the open-drain pin is active, it will drive low. when the pin is inactive, the resistor will pull up the trace to 5.0 v, thereby meeting cmos requirements. the open-drain pin will only drive low or tri-state; it will never drive high. the rise time is dependent on the value of the pull-up resistor and load impedance. the i ol current specification should be considered when selecting a pull-up resistor slew?rate control the output buffer for each max 3000a i/o pin has an adjustable output slew rate that can be configured for low?noise or high?speed performance. a faster slew rate provides high?speed transitions for high-performance systems. however, these fast transitions may introduce noise transients into the system. a slow slew rate reduces system noise, but adds a nominal delay of 4 to 5 ns. when the configuration cell is turned off, the slew rate is set for low?noise performance. each i/o pin has an individual eeprom bit that controls the slew rate, allowing designers to specify the slew rate on a pin?by?pin basis. the slew rate control affects both the rising and falling edges of the output signal. design security all max 3000a devices contain a programmable security bit that controls access to the data programmed into the device. when this bit is programmed, a design implemented in the device cannot be copied or retrieved. this feature provides a high level of design security because programmed data within eeprom cells is invisible. the security bit that controls this function, as well as all other programmed data, is reset only when the device is reprogrammed. generic testing max 3000a devices are fully tested. complete testing of each programmable eeprom bit and all internal logic elements ensures 100 % programming yield. ac test measurements are taken under conditions equivalent to those shown in figure 8 . test patterns can be used and then erased during early stages of the production flow.
18 altera corporation max 3000a programmable logic device family data sheet figure 8. max 3000a ac test conditions operating conditions tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, dc operating conditions, and capacitance for max 3000a devices. v cc to test system c1 (includes jig capacitance) device input rise and fall times < 2 ns device output 703 ? 620 ? [521 ? ] [481 ? ] power supply transients can affect ac measurements. simultaneous transitions of multiple outputs should be avoided for accurate measurement. threshold tests must not be performed under ac conditions. large?amplitude, fast? ground?current transients normally occur as the device outputs discharge the load capacitances. when these transients flow through the parasitic inductance between the device ground pin and the test system ground, significant reductions in observable noise immunity can result. numbers in brackets are for 2.5?v outputs. numbers without brackets are for 3.3?v devices or outputs. table 9. max 3000a device absolute maximum ratings note (1) symbol parameter conditions min max unit v cc supply voltage with respect to ground (2) ?.5 4.6 v v i dc input voltage 2.0 5.75 v i out dc output current, per pin ?5 25 ma t stg storage temperature no bias ?5 150 c t a ambient temperature under bias ?5 135 c t j junction temperature pqfp and tq fp packages, under bias 135 c
altera corporation 19 max 3000a programmable logic device family data sheet table 10. max 3000a device recommended operating conditions symbol parameter conditions min max unit v ccint supply voltage for internal logic and input buffers (10) 3.0 3.6 v v ccio supply voltage for output drivers, 3.3? operation 3.0 3.6 v supply voltage for output drivers, 2.5? operation 2.3 2.7 v v ccisp supply voltage during isp 3.0 3.6 v v i input voltage (3) ?.5 5.75 v v o output voltage 0v ccio v t a ambient temperature for commercial use 0 70 c t j junction temperature for commercial use 0 90 c t r input rise time 40 ns t f input fall time 40 ns table 11. max 3000a device dc operating conditions note (4) symbol parameter conditions min max unit v ih high?evel input voltage 1.7 5.75 v v il lowlevel input voltage 0.5 0.8 v v oh 3.3? high?evel ttl output voltage i oh = 8 ma dc, v ccio = 3.00 v (5) 2.4 v 3.3? high?evel cmos output voltage i oh = 0.1 ma dc, v ccio = 3.00 v (5) v ccio ?0.2 v 2.5? high?evel output voltage i oh = 100 ? dc, v ccio = 2.30 v (5) 2.1 v i oh = 1 ma dc, v ccio = 2.30 v (5) 2.0 v i oh = 2 ma dc, v ccio = 2.30 v (5) 1.7 v v ol 3.3? lowlevel ttl output voltage i ol = 8 ma dc, v ccio = 3.00 v (6) 0.4 v 3.3? lowlevel cmos output voltage i ol = 0.1 ma dc, v ccio = 3.00 v (6) 0.2 v 2.5? lowlevel output voltage i ol = 100 a dc, v ccio = 2.30 v (6) 0.2 v i ol = 1 ma dc, v ccio = 2.30 v (6) 0.4 v i ol = 2 ma dc, v ccio = 2.30 v (6) 0.7 v i i input leakage current v i = ?.5 to 5.5 v (7) ?0 10 a i oz tri?tate output offstate current v i = ?.5 to 5.5 v (7) ?0 10 a r isp value of i/o pin pull?p resistor when programming in?ystem or during power?p v ccio = 2.3 to 3.6 v (8) 20 74 k ?
20 altera corporation max 3000a programmable logic device family data sheet notes to tables: (1) see the operating requirements for altera devices data sheet . (2) minimum dc input voltage is ?0.5 v. during transitions, the inputs may undershoot to ?2.0 v or overshoot to 5.75 v for input currents less than 100 ma and periods shorter than 20 ns. (3) all pins, including dedicated inputs, i/o pins, and jtag pins, may be driven before v ccint and v ccio are powered. (4) these values are specified under the recommended operating conditions, as shown in table 10 on page 19 . (5) the parameter is measured with 50 % of the outputs each sourcing the specified current. the i oh parameter refers to high?level ttl or cmos output current. (6) the parameter is measured with 50 % of the outputs each sinking the specified current. the i ol parameter refers to low?level ttl, pci, or cmos output current. (7) this value is specified during normal device operation. during power-up, the maximum leakage current is 300 a. (8) this pull?up exists while devices are programmed in?system and in unprogrammed devices during power?up. (9) capacitance is measured at 25 c and is sample?tested only. the oe1 pin (high?voltage pin during programming) has a maximum capacitance of 20 pf. (10) the por time for all max 3000a devices does not exceed 100 s. the sufficient v ccint voltage level for por is 3.0 v. the device is fully initialized within the por time after v ccint reaches the sufficient por voltage level. figure 9 shows the typical output drive characteristics of max 3000a devices. table 12. max 3000a device capacitance note (9) symbol parameter conditions min max unit c in input pin capacitance v in = 0 v, f = 1.0 mhz 8 pf c i/o i/o pin capacitance v out = 0 v, f = 1.0 mhz 8 pf
altera corporation 21 max 3000a programmable logic device family data sheet figure 9. output drive characteristics of max 3000a devices power sequencing & hot?socketing because max 3000a devices can be used in a mixed?voltage environment, they have been designed specifically to tolerate any possible power?up sequence. the v ccio and v ccint power planes can be powered in any order. signals can be driven into max 3000a devices before and during power-up without damaging the device. in addition, max 3000a devices do not drive out during power-up. once operating conditions are reached, max 3000a devices operate as specified by the user. v o output voltage (v) 1234 0 0 50 i ol i oh v ccint = 3.3 = 25 c v v cci o = 3.3 v temperature 100 150 typical i output current (ma) o v o output voltage (v) 1234 v ccint = 3.3 v v cci o = 2.5 v i oh 2.5 v 3.3 v typical i output current (ma) o 0 0 50 i ol 100 150 o = 25 c temperature o
22 altera corporation max 3000a programmable logic device family data sheet timing model max 3000a device timing can be analyzed with the altera software, with a variety of popular industry?standard eda simulators and timing analyzers, or with the timing model shown in figure 10 . max 3000a devices have predictable internal delays that enable the designer to determine the worst?case timing of any design. the software provides timing simulation, point?to?point delay prediction, and detailed timing analysis for device?wide performance evaluation. figure 10. max 3000a timing model the timing characteristics of any signal path can be derived from the timing model and parameters of a particular device. external timing parameters, which represent pin?to?pin timing delays, can be calculated as the sum of internal parameters. figure 11 shows the timing relationship between internal and external delay parameters. logic array delay t lad output delay t od3 t od2 t od1 t xz z t x1 t zx2 t zx3 input delay t in register delay t su t h t pre t clr t rd t comb pia delay t pia shared expander delay t sexp register control delay t lac t ic t en i/o delay t io global control delay t glob internal output enable delay t ioe parallel expander delay t pexp
altera corporation 23 max 3000a programmable logic device family data sheet figure 11. max 3000a switching waveforms combinatorial mode input pin i/o pin pia delay shared expander delay logic array input parallel expander delay logic array output output pin t in t lac , t lad t pia t od t pexp t io t sexp t comb global clock mode global clock pin global clock at register data or enable (logic array output) t f t ch t cl t r t in t glob t su t h array clock mode input or i/o pin clock into pia clock into logic array clock at register data from logic array register to pia to logic array register output to pin t f t r t ach t acl t su t in t io t rd t pia t clr , t pre t h t pia t ic t pia t od t od t r & t f < 2 ns. inputs are driven at 3 v for a logic high and 0 v for a logic low. all timing characteristics are measured at 1.5 v.
24 altera corporation max 3000a programmable logic device family data sheet tables 13 through 20 show epm3032a, epm3064a, epm3128a, epm3256a, and epm3512a timing information. table 13. epm3032a external timing parameters note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max t pd1 input to non registered output c1 = 35 pf (2) 4.5 7.5 10 ns t pd2 i/o input to non registered output c1 = 35 pf (2) 4.5 7.5 10 ns t su global clock setup time (2) 2.9 4.7 6.3 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.0 1.0 5.0 1.0 6.7 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.6 2.5 3.6 ns t ah array clock hold time (2) 0.3 0.5 0.5 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.3 1.0 7.2 1.0 9.4 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 4.4 7.2 9.7 ns f cnt maximum internal global clock frequency (2) , (4) 227.3 138.9 103.1 mhz t acnt minimum array clock period (2) 4.4 7.2 9.7 ns f acnt maximum internal array clock frequency (2) , (4) 227.3 138.9 103.1 mhz
altera corporation 25 max 3000a programmable logic device family data sheet table 14. epm3032a internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max t in input pad and buffer delay 0.7 1.2 1.5 ns t io i/o input pad and buffer delay 0.7 1.2 1.5 ns t sexp shared expander delay 1.9 3.1 4.0 ns t pexp parallel expander delay 0.5 0.8 1.0 ns t lad logic array delay 1.5 2.5 3.3 ns t lac logic control array delay 0.6 1.0 1.2 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.3 1.8 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 1.3 1.8 2.3 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.3 6.8 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.3 2.0 2.8 ns t h register hold time 0.6 1.0 1.3 ns t rd register delay 0.7 1.2 1.5 ns t comb combinatorial delay 0.6 1.0 1.3 ns t ic array clock delay 1.2 2.0 2.5 ns t en register enable time 0.6 1.0 1.2 ns t glob global control delay 0.8 1.3 1.9 ns t pre register preset time 1.2 1.9 2.6 ns
26 altera corporation max 3000a programmable logic device family data sheet t clr register clear time 1.2 1.9 2.6 ns t pia pia delay (2) 0.9 1.5 2.1 ns t lpa low?ower adder (5) 2.5 4.0 5.0 ns table 15. epm3064a external timing parameters note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max t pd1 input to non?egistered output c1 = 35 pf (2) 4.5 7.5 10.0 ns t pd2 i/o input to nonregistered output c1 = 35 pf (2) 4.5 7.5 10.0 ns t su global clock setup time (2) 2.8 4.7 6.2 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.1 1.0 5.1 1.0 7.0 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.6 2.6 3.6 ns t ah array clock hold time (2) 0.3 0.4 0.6 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.3 1.0 7.2 1.0 9.6 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 4.5 7.4 10.0 ns f cnt maximum internal global clock frequency (2) , (4) 222.2 135.1 100.0 mhz t acnt minimum array clock period (2) 4.5 7.4 10.0 ns f acnt maximum internal array clock frequency (2) , (4) 222.2 135.1 100.0 mhz table 14. epm3032a internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max
altera corporation 27 max 3000a programmable logic device family data sheet table 16. epm3064a internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max t in input pad and buffer delay 0.6 1.1 1.4 ns t io i/o input pad and buffer delay 0.6 1.1 1.4 ns t sexp shared expander delay 1.8 3.0 3.9 ns t pexp parallel expander delay 0.4 0.7 0.9 ns t lad logic array delay 1.5 2.5 3.2 ns t lac logic control array delay 0.6 1.0 1.2 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.3 1.8 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 1.3 1.8 2.3 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.3 6.8 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.3 2.0 2.9 ns t h register hold time 0.6 1.0 1.3 ns t rd register delay 0.7 1.2 1.6 ns t comb combinatorial delay 0.6 0.9 1.3 ns t ic array clock delay 1.2 1.9 2.5 ns t en register enable time 0.6 1.0 1.2 ns t glob global control delay 1.0 1.5 2.2 ns t pre register preset time 1.3 2.1 2.9 ns t clr register clear time 1.3 2.1 2.9 ns
28 altera corporation max 3000a programmable logic device family data sheet t pia pia delay (2) 1.0 1.7 2.3 ns t lpa low?ower adder (5) 3.5 4.0 5.0 ns table 17. epm3128a external timing parameters note (1) symbol parameter conditions speed grade unit ?5 ?7 ?10 min max min max min max t pd1 input to non registered output c1 = 35 pf (2) 5.0 7.5 10 ns t pd2 i/o input to non registered output c1 = 35 pf (2) 5.0 7.5 10 ns t su global clock setup time (2) 3.3 4.9 6.6 ns t h global clock hold time (2) 0.0 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 3.4 1.0 5.0 1.0 6.6 ns t ch global clock high time 2.0 3.0 4.0 ns t cl global clock low time 2.0 3.0 4.0 ns t asu array clock setup time (2) 1.8 2.8 3.8 ns t ah array clock hold time (2) 0.2 0.3 0.4 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 4.9 1.0 7.1 1.0 9.4 ns t ach array clock high time 2.0 3.0 4.0 ns t acl array clock low time 2.0 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 2.0 3.0 4.0 ns t cnt minimum global clock period (2) 5.2 7.7 10.2 ns f cnt maximum internal global clock frequency (2) , (4) 192.3 129.9 98.0 mhz t acnt minimum array clock period (2) 5.2 7.7 10.2 ns f acnt maximum internal array clock frequency (2) , (4) 192.3 129.9 98.0 mhz table 16. epm3064a internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit ?4 ?7 ?10 min max min max min max
altera corporation 29 max 3000a programmable logic device family data sheet table 18. epm3128a internal timing parameters (part 1 of 2) note (1) symbol parameter conditions speed grade unit ?5 ?7 ?10 min max min max min max t in input pad and buffer delay 0.7 1.0 1.4 ns t io i/o input pad and buffer delay 0.7 1.0 1.4 ns t sexp shared expander delay 2.0 2.9 3.8 ns t pexp parallel expander delay 0.4 0.7 0.9 ns t lad logic array delay 1.6 2.4 3.1 ns t lac logic control array delay 0.7 1.0 1.3 ns t ioe internal output enable delay 0.0 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 0.8 1.2 1.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 1.3 1.7 2.1 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 5.8 6.2 6.6 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 4.5 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 4.0 5.0 ns t su register setup time 1.4 2.1 2.9 ns t h register hold time 0.6 1.0 1.3 ns t rd register delay 0.8 1.2 1.6 ns t comb combinatorial delay 0.5 0.9 1.3 ns t ic array clock delay 1.2 1.7 2.2 ns t en register enable time 0.7 1.0 1.3 ns t glob global control delay 1.1 1.6 2.0 ns t pre register preset time 1.4 2.0 2.7 ns t clr register clear time 1.4 2.0 2.7 ns
30 altera corporation max 3000a programmable logic device family data sheet t pia pia delay (2) 1.4 2.0 2.6 ns t lpa low?ower adder (5) 4.0 4.0 5.0 ns table 19. epm3256a external timing parameters note (1) symbol parameter conditions speed grade unit ?7 ?10 min max min max t pd1 input to non?egistered output c1 = 35 pf (2) 7.5 10 ns t pd2 i/o input to non?egistered output c1 = 35 pf (2) 7.5 10 ns t su global clock setup time (2) 5.2 6.9 ns t h global clock hold time (2) 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 4.8 1.0 6.4 ns t ch global clock high time 3.0 4.0 ns t cl global clock low time 3.0 4.0 ns t asu array clock setup time (2) 2.7 3.6 ns t ah array clock hold time (2) 0.3 0.5 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 7.3 1.0 9.7 ns t ach array clock high time 3.0 4.0 ns t acl array clock low time 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 4.0 ns t cnt minimum global clock period (2) 7.9 10.5 ns f cnt maximum internal global clock frequency (2) , (4) 126.6 95.2 mhz t acnt minimum array clock period (2) 7.9 10.5 ns f acnt maximum internal array clock frequency (2) , (4) 126.6 95.2 mhz table 18. epm3128a internal timing parameters (part 2 of 2) note (1) symbol parameter conditions speed grade unit ?5 ?7 ?10 min max min max min max
altera corporation 31 max 3000a programmable logic device family data sheet table 20. epm3256a internal timing parameters note (1) symbol parameter conditions speed grade unit ?7 ?10 min max min max t in input pad and buffer delay 0.9 1.2 ns t io i/o input pad and buffer delay 0.9 1.2 ns t sexp shared expander delay 2.8 3.7 ns t pexp parallel expander delay 0.5 0.6 ns t lad logic array delay 2.2 2.8 ns t lac logic control array delay 1.0 1.3 ns t ioe internal output enable delay 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 1.2 1.6 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 1.7 2.1 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 6.2 6.6 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 5.0 ns t su register setup time 2.1 2.9 ns t h register hold time 0.9 1.2 ns t rd register delay 1.2 1.6 ns t comb combinatorial delay 0.8 1.2 ns t ic array clock delay 1.6 2.1 ns t en register enable time 1.0 1.3 ns t glob global control delay 1.5 2.0 ns t pre register preset time 2.3 3.0 ns t clr register clear time 2.3 3.0 ns t pia pia delay (2) 2.4 3.2 ns t lpa low?ower adder (5) 4.0 5.0 ns
32 altera corporation max 3000a programmable logic device family data sheet table 21. epm3512a external timing parameters note (1) symbol parameter conditions speed grade unit -7 -10 min max min max t pd1 input to non-registered output c1 = 35 pf (2) 7.5 10.0 ns t pd2 i/o input to non-registered output c1 = 35 pf (2) 7.5 10.0 ns t su global clock setup time (2) 5.6 7.6 ns t h global clock hold time (2) 0.0 0.0 ns t fsu global clock setup time of fast input 3.0 3.0 ns t fh global clock hold time of fast input 0.0 0.0 ns t co1 global clock to output delay c1 = 35 pf 1.0 4.7 1.0 6.3 ns t ch global clock high time 3.0 4.0 ns t cl global clock low time 3.0 4.0 ns t asu array clock setup time (2) 2.5 3.5 ns t ah array clock hold time (2) 0.2 0.3 ns t aco1 array clock to output delay c1 = 35 pf (2) 1.0 7.8 1.0 10.4 ns t ach array clock high time 3.0 4.0 ns t acl array clock low time 3.0 4.0 ns t cppw minimum pulse width for clear and preset (3) 3.0 4.0 ns t cnt minimum global clock period (2) 8.6 11.5 ns f cnt maximum internal global clock frequency (2) , (4) 116.3 87.0 mhz t acnt minimum array clock period (2) 8.6 11.5 ns f acnt maximum internal array clock frequency (2) , (4) 116.3 87.0 mhz table 22. epm3512a internal timing parameters (part 1 of 3) note (1) symbol parameter conditions speed grade unit -7 -10 min max min max t in input pad and buffer delay 0.7 0.9 ns t io i/o input pad and buffer delay 0.7 0.9 ns t fin fast input delay 3.1 3.6 ns
altera corporation 33 max 3000a programmable logic device family data sheet t sexp shared expander delay 2.7 3.5 ns t pexp parallel expander delay 0.4 0.5 ns t lad logic array delay 2.2 2.8 ns t lac logic control array delay 1.0 1.3 ns t ioe internal output enable delay 0.0 0.0 ns t od1 output buffer and pad delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 1.0 1.5 ns t od2 output buffer and pad delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 1.5 2.0 ns t od3 output buffer and pad delay, slow slew rate = on v ccio = 2.5 v or 3.3 v c1 = 35 pf 6.0 6.5 ns t zx1 output buffer enable delay, slow slew rate = off v ccio = 3.3 v c1 = 35 pf 4.0 5.0 ns t zx2 output buffer enable delay, slow slew rate = off v ccio = 2.5 v c1 = 35 pf 4.5 5.5 ns t zx3 output buffer enable delay, slow slew rate = on v ccio = 3.3 v c1 = 35 pf 9.0 10.0 ns t xz output buffer disable delay c1 = 5 pf 4.0 5.0 ns t su register setup time 2.1 3.0 ns t h register hold time 0.6 0.8 ns t fsu register setup time of fast input 1.6 1.6 ns t fh register hold time of fast input 1.4 1.4 ns t rd register delay 1.3 1.7 ns t comb combinatorial delay 0.6 0.8 ns t ic array clock delay 1.8 2.3 ns t en register enable time 1.0 1.3 ns t glob global control delay 1.7 2.2 ns t pre register preset time 1.0 1.4 ns t clr register clear time 1.0 1.4 ns t pia pia delay (2) 3.0 4.0 ns table 22. epm3512a internal timing parameters (part 2 of 3) note (1) symbol parameter conditions speed grade unit -7 -10 min max min max
34 altera corporation max 3000a programmable logic device family data sheet notes to tables: (1) these values are specified under the recommended operating conditions, as shown in table 10 on page 19 . see figure 11 on page 23 for more information on switching waveforms. (2) these values are specified for a pia fan?out of one lab (16 macrocells). for each additional lab fan?out in these devices, add an additional 0.1 ns to the pia timing value. (3) this minimum pulse width for preset and clear applies for both global clear and array controls. the t lpa parameter must be added to this minimum width if the clear or reset signal incorporates the t lad parameter into the signal path. (4) these parameters are measured with a 16?bit loadable, enabled, up/down counter programmed into each lab. (5) the t lpa parameter must be added to the t lad , t lac , t ic , t en , t sexp , t acl , and t cppw parameters for macrocells running in low?power mode. power consumption supply power (p) versus frequency ( f max , in mhz) for max 3000a devices is calculated with the following equation: p = p int + p io = i ccint v cc + p io the p io value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in application note 74 (evaluating power for altera devices) . the i ccint value depends on the switching frequency and the application logic. the i ccint value is calculated with the following equation: i ccint = (a mc ton ) + [b (mc dev ? mc ton )] + (c mc used f max tog lc ) the parameters in the i ccint equation are: t lpa low-power adder (5) 4.5 5.0 ns table 22. epm3512a internal timing parameters (part 3 of 3) note (1) symbol parameter conditions speed grade unit -7 -10 min max min max
altera corporation 35 max 3000a programmable logic device family data sheet mc ton = number of macrocells with the turbo bit tm option turned on, as reported in the max+plus ii report file ( .rpt ) mc dev = number of macrocells in the device mc used = total number of macrocells in the design, as reported in the rpt file f max = highest clock frequency to the device tog lc = average percentage of logic cells toggling at each clock (typically 12.5 % ) a, b, c = constants (shown in table 23 ) the i ccint calculation provides an i cc estimate based on typical conditions using a pattern of a 16?bit, loadable, enabled, up/down counter in each lab with no output load. actual i cc should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. figures 12 and 13 show the typical supply current versus frequency for max 3000a devices. table 23. max 3000a i cc equation constants device a b c epm3032a 0.85 0.36 0.017 epm3064a 0.85 0.36 0.017 epm3128a 0.85 0.36 0.017 epm3256a 0.85 0.36 0.017 epm3512a 0.85 0.36 0.017
36 altera corporation max 3000a programmable logic device family data sheet figure 12. i cc vs. frequency for max 3000a devices epm3032a v cc = 3.3 v frequency (mhz) 60 80 120 140 v cc = 3.3 v room temperature room temperature 0 frequency (mhz) high speed non-turbo 50 100 1 5 0 200 222.2 mhz 125.0 mhz 250 0 50 100 1 5 0 200 250 epm3064a 20 100 40 30 40 60 70 high speed non-turbo 227.3 mhz 144.9 mhz 10 50 20 typical i active (ma) cc typical i active (ma) cc
altera corporation 37 max 3000a programmable logic device family data sheet figure 13. i cc vs. frequency for max 3000a devices epm3128a v cc = 3.3 v room temperature frequency (mhz) 150 200 300 350 v cc = 3.3 v room temperature room temperature 0 frequency (mhz) high speed non-turbo 50 100 150 200 172.4 mhz 102.0 mhz 0 50 100 150 200 250 epm3256a 50 250 100 90 120 180 210 high speed non-turbo 192.3 mhz 108.7 mhz 30 150 60 typical i active (ma) cc typical i active (ma) cc epm3512a v cc = 3.3 v frequency (mhz) low power 116.3 mhz 76.3 mhz 100 200 300 400 500 600 0 20 40 80 100 typical i active (ma) cc high speed 60 120 140
38 altera corporation max 3000a programmable logic device family data sheet device pin?outs see the altera web site ( http://www.altera.com ) or the altera digital library for pin?out information. figures 14 through 18 show the package pin?out diagrams for max 3000a devices. figure 14. 44?pin plcc/tqfp package pin?out diagram package outlines not drawn to scale. 44-pin plcc i/o i/o i/o vcc input/oe2/gclk2 input/gclrn input/oe1 input/gclk1 gnd i/o i/o i/o i/o/tdo i/o gnd vcc i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o 6 5 4 3 2 1 44 43 42 41 40 18 19 20 21 22 23 24 25 26 27 28 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 34 33 32 31 30 29 epm3032a epm3064a i/o/tdi i/o i/o gnd i/o i/o i/o/tms i/o vcc i/o gnd 44-pin tqfp pin 12 pin 23 pin 34 pin 1 i/o i/o i/o vcc input/oe2/gclk2 input/gclrn input/oe1 input/gclk1 gnd i/o i/o i/o i/o/tdo i/o gnd vcc i/o i/o i/o/tck i/o gnd i/o i/o i/o i/o i/o gnd vcc i/o i/o i/o i/o i/o i/o/tdi i/o i/o gnd i/o i/o i/o/tms i/o vcc i/o gnd epm3032a epm3064a
altera corporation 39 max 3000a programmable logic device family data sheet figure 15. 100?pin tqfp package pin?out diagram package outline not drawn to scale. figure 16. 144?pin tqfp package pin?out diagram package outline not drawn to scale . pin 1 pin 26 pin 7 6 pin 5 1 epm3064a epm3128a indicates location of pin 1 pin 1 pin 109 pin 7 3 pin 37 epm3128a epm3256a
40 altera corporation max 3000a programmable logic device family data sheet figure 17. 208?pin pqfp package pin?out diagram package outline not drawn to scale . pin 1 pin 157 pin 105 pin 53 epm3256a epm3512a
altera corporation 41 max 3000a programmable logic device family data sheet figure 18. 256-pin fineline bga package pin-out diagram package outline not drawn to scale . revision history the information contained in the max 3000a programmable logic device data sheet version 3.2 supersedes information published in previous versions. the following changes were made in the max 3000a programmable logic device data sheet version 3.2: version 3.2 updated the epm3512 icc versus frequency graph in figure 13 . version 3.1 the following changes were made in the max 3000a programmable logic device data sheet version 3.1: updated timing information in table 1 for the epm3256a device. updated note (10) of table 12 . indicates location of ball a1 a1 ball pad corner g f e d c b a h j k l m n p r t 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 epm3512a
copyright ? 2002 altera corporation. all rights reserved. altera, the programmable solutions company, th e stylized altera logo, specific device designations, and all other words and logos that are identified a s trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of alter a corporation in the u.s. and other countries. all other product or service names are the property of the ir respective holders. altera products are protected under numerous u.s. and foreign patents and pendin g applications, maskwork rights, and copyrights. altera warrants performance of its semiconductor products t o current specifications in accordance with altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by altera corporation. altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services 1 01 innovation drive s an jose, ca 95134 ( 408) 544-7000 h ttp://www.altera.com a pplications hotline: ( 800) 800-epld c ustomer marketing: ( 408) 544-7104 l iterature services: l it_req@altera.com max 3000a programmable logic device family data sheet 42 altera corporation version 3.0 the following changes were made in the max 3000a programmable logic device data sheet version 3.0: added epm3512a device. updated tables 2 and 3 .

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